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* pin 3 is the anode of the internal led and must be left unconnected for guaranteed data sheet performance. pin 7 is not connected internally. ** a 0.1 f bypass capacitor must be connected between pins 1 and 4, and 5 and 8. features ? +5 v cmos compatibility ? 20 ns maximum prop. delay skew ? high speed: 25 mbd ? 40 ns max. prop. delay ? 10 kv/s minimum common mode rejection ? C40 to 85c temperature range ? safety and regulatory approvals ul recognized C 3750 v rms for 1 min. per ul 1577 C 5000 v rms for 1 min. per ul 1577 (for hcpl-772x option 020) csa component acceptance notice #5 iec/en/din en 60747-5-5 C v iorm = 630 v peak for hcpl-772x option 060 C v iorm = 567 v peak for hcpl-072x option 060 applications ? digital feldbus isolation: cc-link, devicenet, prof - bus, sds ? ac plasma display panel level shifting ? multiplexed data transmission ? computer peripheral interface ? microprocessor system interface caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. hcpl-0720, hcpl-7720, hcpl-0721 and hcpl-7721 40 ns propagation delay, cmos optocoupler data sheet truth table positive logic v i led1 v o output h off h l on l 8 7 6 1 3 shield 5 2 4 **v dd1 v i * gnd 1 v dd2 ** v o gnd 2 v i , input led1 h l off on truth table (positive logic) nc* i o led1 v o , output h l lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product description available in either an 8-pin dip or so-8 package style respectively, the hcpl-772x or hcpl-072x optocouplers utilize the latest cmos ic technology to achieve out - standing performance with very low power consump - tion. the hcpl-772x/072x require only two bypass ca - pacitors for complete cmos compatability. basic building blocks of the hcpl-772x/072x are a cmos led driver ic, a high speed led and a cmos detector ic. a cmos logic input signal controls the led driver ic which supplies current to the led. the detector ic incor - porates an integrated photodiode, a high-speed tran - simpedance amplifer, and a voltage comparator with an output driver. functional diagram
2 selection guide 8-pin dip small outline (300 mil) so-8 data rate pwd hcpl-7721 hcpl-0721 25 mb 6 ns hcpl-7720 hcpl-0720 25 mb 8 ns ordering information hcpl-0720, hcpl-0721, hcpl-7720 and hcpl-7721 are ul recognized with 3750 v rms for 1 minute per ul1577. option part rohs non rohs surface gull tape ul 5000 v rms / iec/en/din number compliant compliant package mount wing & reel 1 minute rating en 60747-5-5 quantity -000e no option 50 per tube -300e #300 x x 50 per tube -500e #500 x x x 1000 per reel hcpl-7720 -020e -020 300 mil x 50 per tube hcpl-7721 -320e -320 dip-8 x x x 50 per tube -520e -520 x x x x 1000 per reel -060e #060 x 50 per tube -360e #360 x x x 50 per tube -560e #560 x x x x 1000 per reel -000e no option x x 100 per tube hcpl-0720 -500e #500 so-8 x x x 1500 per reel hcpl-0721 -060e #060 x x x 100 per tube -560e #560 x x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: hcpl-7720-560e to order product of gull wing surface mount package in tape and reel packaging with iec/en/din en 60747-5-5 safety approval and rohs compliant. example 2: hcpl-0721 to order product of small outline so-8 package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since july 15, 2001 and rohs compliant will use Cxxxe.
3 package outline drawing hcpl-772x 8-pin dip package 9.65 0.25 (0.380 0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxv yyww date code 1.080 0.320 (0.043 0.013) 2.54 0.25 (0.100 0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5 typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 0.25 (0.300 0.010) 6.35 0.25 (0.250 0.010) type number *option 300 and 500 not marked. note: floating lead protrusion is 0.25 mm (10 mils) max. option 060 code* 3.56 0.13 (0.140 0.005)
4 package outline drawing hcpl-772x package with gull wing surface mount option 300 package outline drawing hcpl-072x outline drawing (small outline so-8 package) 0.635 0.25 (0.025 0.010) 12 nom. 9.65 0.25 (0.380 0.010) 0.635 0.130 (0.025 0.005) 7.62 0.25 (0.300 0.010) 5 6 7 8 4 3 2 1 9.65 0.25 (0.380 0.010) 6.350 0.25 (0.250 0.010) 1.016 (0.040) 1.27 (0.050) 10.9 (0.430) 2.0 (0.080) land pattern recommendation 1.080 0.320 (0.043 0.013) 3.56 0.13 (0.140 0.005) 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). note: floating lead protrusion is 0.25 mm (10 mils) max. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) xxxv yww 8 7 6 5 4 3 2 1 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.406 0.076 (0.016 0.003) 1.270 (0.050) bsc 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 0.254 (0.205 0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. option number 500 not marked. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.203 0.102 (0.008 0.004) 7 pin one 0 ~ 7 * * 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation
5 all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimen sions are needed as a starting point for the equip - ment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance require - ments must be met as specifed for individual equipment standards. for creepage, the shortest distance path along insulation and safety related specifcations value parameter symbol 772x 072x units conditions minimum external air l(i01) 7.1 4.9 mm measured from input terminals to output gap (clearance) terminals, shortest distance through air. minimum external l(i02) 7.4 4.8 mm measured from input terminals to output tracking (creepage) terminals, shortest distance path along body. minimum internal plastic 0.08 0.08 mm insulation thickness between emitter and gap (internal clearance) detector; also known as distance through insulation. tracking resistance cti 175 175 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia material group (din vde 0110, 1/89, table 1) the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on fac - tors such as pollution degree and insulation level. regulatory information the hcpl-772x/072x have been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 60747-5-5 solder refow thermal profle recommended refow condition as per jedec standard, j-std-020 (latest revision). non- halide flux should be used.
6 iec/en/din en 60747-5-5 insulation characteristics* (option 060) characteristic hcpl-7720 hcpl-0720 description symbol hcpl-7721 hcpl-0721 unit installation classifcation per din vde 0110, table 1 for rated mains voltage 150 v rms i-iv i-iv for rated mains voltage 300 v rms i-iv i-iii for rated mains voltage 600 v rms i-iv i-iii climatic classifcation 55/85/21 55/85/21 pollution degree (din vde 0110/39) 2 2 maximum working insulation voltage v iorm 630 567 v peak input-to-output test voltage, method b* v pr 1181 1063 v peak v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc input-to-output test voltage, method a* v pr 1008 907 v peak v iorm x 1.6 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc highest allowable overvoltage v iotm 8000 6000 v peak (transient overvoltage, t ini = 60 sec) safety limiting values C maximum values allowed in the event of a failure case temperature t s 175 150 c input current i s,input 230 150 ma output power p s,output 600 600 mw insulation resistance at t s , v 10 = 500 v r io 10 9 10 9 * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (iec/ en/din en 60747-5-5) for a detailed description of method a and method b partial discharge test profles. note: these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. the surface mount classifcation is class a in accordance with cecc 00802. absolute maximum ratings parameter symbol min. max. units figure storage temperature t s C55 125 c ambient operating temperature [1] t a C40 +85 c supply voltages v dd1 , v dd2 0 6.0 volts input voltage v i C0.5 v dd1 +0.5 volts output voltage v o C0.5 v dd2 +0.5 volts average output current i o 10 ma lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refow temperature profle see solder refow temperature profle section recommended operating conditions parameter symbol min. max. units figure ambient operating temperature t a C40 +85 c supply voltages v dd1 , v dd2 4.5 5.5 v logic high input voltage v ih 2.0 v dd1 v 1, 2 logic low input voltage v il 0.0 0.8 v input signal rise and fall times t r , t f 1.0 ms
7 electrical specifcations test conditions that are not specifed can be anywhere within the recommended operating range. all typical specifcations are at t a = +25 c, v dd1 = v dd2 = +5 v. parameter symbol min. typ. max. units test conditions fig. note dc specifcations logic low input i dd1l 6.0 10.0 ma v i = 0 v 2 supply current logic high input i dd1h 1.5 3.0 ma v i = v dd1 supply current output supply current i dd2l 5.5 9.0 ma i dd2h 7.0 9.0 input current i i C10 10 a logic high output v oh 4.4 5.0 v i o = -20 a, v i = v ih 1, 2 voltage 4.0 4.8 i o = -4 ma, v i = v ih logic low output v ol 0 0.1 v i o = 20 a, v i = v il voltage 0.1 v i o = 400 a, v i = v il 0.5 1.0 i o = 4 ma, v i = v il switching specifcations propagation delay time t phl 20 40 ns c l = 15 pf 3, 6 3 to logic low output cmos signal levels propagation delay time t plh 23 40 ns to logic high output pulse width pw 40 ns data rate 25 mbd pulse width distortion pwd 7721/0721 3 6 ns 7 4 |t phl - t plh | 7720/0720 3 8 ns propagation delay skew t psk 20 5 output rise time t r 9 ns (10 - 90%) output fall time t f 8 ns (90 - 10%) common mode |cm h | 10 20 kv/ s v i = v dd1 , v o > 6 transient immunity at 0.8 v dd1 , logic high output v cm = 1000 v common mode |cm l | 10 20 v i = 0 v, v o > 0.8 v, transient immunity at v cm = 1000 v logic low output input dynamic power c pd1 60 pf 7 dissipation capacitance output dynamic power c pd2 10 dissipation capacitance
8 notes: 1. absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. it does not guarantee functionality. 2. the led is on when v i is low and off when v i is high. 3. t phl propagation delay is measured from the 50% level on the falling edge of the v i signal to the 50% level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the rising edge of the v i signal to the 50% level of the rising edge of the v o signal. 4. pwd is defned as |t phl - t plh |. %pwd (percent pulse width distortion) is equal to the pwd divided by pulse width. 5. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 6. cm h is the maximum common mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. unloaded dynamic power dissipation is calculated as follows: c pd * v dd2 * f + i dd * v dd , where f is switching frequency in mhz. 8. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 9. in accordance with ul1577, each hcpl-072x is proof tested by applying an insulation test voltage 4500 v rms for 1 second (leakage detection current limit, i i-o 5 a). each hcpl-772x is proof tested by applying an insulation test voltage 4500 vrms for 1 second (leakage detection current limit. i i-o 5 a.) 10. the input-output momentary with stand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to your equipment level safety specifcation or avago application note 1074 optocou - pler input-output endurance voltage. 11. c i is the capacitance measured at pin 2 (v i ). figure 1. typical output voltage vs. input volt - age figure 2. typical input voltage switching thresh - old vs. input supply voltage figure 3. typical propagation delays vs. tem - perature package characteristics parameter symbol min. typ. max. units test conditions fig. note input-output momentary 072x v iso 3750 vrms rh 50%, 8, 9, withstand voltage 772x 3750 t = 1 min., 10 option 020 5000 t a = 25c resistance r i-o 10 12 v i-o = 500 vdc 8 (input-output) capacitance c i-o 0.6 pf f = 1 mhz (input-output) input capacitance c i 3.0 11 input ic junction-to-case -772x jci 145 c/w thermocouple thermal resistance -072x 160 located at center output ic junction-to-case -772x jco 140 underside of package thermal resistance -072x 135 package power dissipation p pd 150 mw v o (v) 0 0 v i (v) 5 4 1 4 1 2 3 5 3 2 0 c 25 c 85 c v ith (v) 4.5 1.6 v dd1 (v) 5.5 2.1 1.7 5.25 4.75 5 2.2 2.0 1.8 1.9 0 c 25 c 85 c t plh , t phl (ns) 0 15 t a (c) 80 27 17 60 20 30 29 25 19 21 10 40 50 70 23 t plh t phl
9 figure 4. typical pulse width distortion vs. temperature figure 5. typical rise time vs. temperature figure 6. typical fall time vs. temperature figure 7. typical propagation delays vs. output load capacitance figure 8. typical pulse width distortion vs. output load capacitance figure 9. thermal derating curve, dependence of safety limiting value with case temperature per iec/en/din en 60747-5-5. pwd (ns) 0 0 t a (c) 80 3 60 20 4 1 40 2 t r (ns) 0 8 t a (c) 80 10 60 20 11 9 40 t f (ns) 0 2 t a (c) 80 6 60 20 7 3 40 5 4 t plh , t phl (ns) 15 15 c i (pf) 50 27 40 29 17 30 23 21 25 20 35 45 19 25 t plh t phl pwd (ns) 15 0 c i (pf) 50 5 40 6 1 30 3 25 20 35 45 2 4 output power ? p s , input current ? i s 0 0 t a ? case temperature ? c 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 175 (230) p s (mw) i s (ma) standard 8 pin dip product output power ? p s , input current ? i s 0 0 t a ? case temperature ? c 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 175 (150) p s (mw) i s (ma) surface mount so8 product
10 application information bypassing and pc board layout the hcpl-772x/072x optocouplers are extremely easy to use. no external interface circuitry is required because the hcpl-772x/072x use high-speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. as shown in figure 10, the only external components required for proper operation are two bypass capacitors. ca - pacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 11 illustrates the recommended printed circuit board layout for the hpcl-772x/072x. figure 10. recommended printed circuit board layout. figure 11. recommended printed circuit board layout propagation delay, pulse-width distortion and propagation delay skew propagation delay is a fgure of merit that describes how quickly a logic signal propagates through a system. the propaga tion delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. see figure 12. figure 12. input t plh t phl output v i v o 10% 90% 90% 10% v oh v ol 0 v 50% 5 v cmos 2.5 v cmos hcpl-0710 fig 13 v dd2 c1 c2 72x yww v o gnd 2 v dd1 v i gnd 1 c1, c2 = 0.01 f to 0.1 f 7 5 6 8 2 3 4 1 gnd 2 c1 c2 nc v dd2 nc v o v dd1 v i 72x yww c1, c2 = 0.01 f to 0.1 f gnd 1
11 figure 13. propagation delay skew waveform. figure 14. parallel data transmission example. propagation delay skew repre sents the uncertainty of where an edge might be after being sent through an op - tocoupler. figure 14 shows that there will be uncertainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these consider - ations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . pulse-width distortion (pwd) is the diference between t phl and t plh and often determines the maxi mum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being trans mitted. typical - ly, pwd on the order of 20 - 30% of the minimum pulse width is tolerable. propagation delay skew, t psk , is an important parameter to con sider in parallel data applications where synchro - nization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of opto - couplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at difer - ent times. if this diference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. propagation delay skew is defned as the diference be - tween the minimum and maximum propa gation delays, either t plh or t phl , for any given group of optocoup lers which are operating under the same conditions (i.e., the same drive current, supply volt age, output load, and op - erating temperature). as illustrated in figure 13, if the in - puts of a group of optocouplers are switched either on or off at the same time, t psk is the diference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 14 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the opto - couplers. the fgure shows data and clock signals at the inputs and outputs of the optocouplers. in this case the data is assumed to be clocked of of the rising edge of the clock. a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the hcpl-772x/072x optocouplers ofer the advantage of guaranteed specifcations for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t psk t psk
12 figure 15. typical feld bus communication physical model digital field bus communication networks to date, despite its many draw backs, the 4 - 20 ma ana - log current loop has been the most widely accepted standard for implementing process control systems. in todays manufacturing environment, however, automat - ed systems are expected to help manage the process, not merely monitor it. with the advent of digital feld bus communication networks such as cc-link, devicenet, profibus, and smart distributed systems (sds), gone are the days of constrained information. controllers can now receive multiple readings from feld devices (sen - sors, actuators, etc.) in addition to diagnostic informa - tion. the physical model for each of these digital feld bus communica tion networks is very similar as shown in figure 15. each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or ac - tuating devices. controller transceiver optical isolation bus interface transceiver optical isolation bus interface transceiver optical isolation bus interface transceiver optical isolation bus interface transceiver optical isolation bus interface field bus xxxxxx yyy sensor device configuration motor starter motor controller
13 optical isolation for field bus networks to recognize the full benefts of these networks, avago optocouplers are recom mended to provide galvanic iso - lation. as network communication is bi-directional (in - volving receiving data from and transmitting data onto the network), two avago optocouplers are needed. by providing galvanic isolation, data integrity is retained via noise reduction and the elimination of false signals. in addition, the network receives maximum protection from power system faults and ground loops. within an isolated node, such as the devicenet node shown in figure 16, some of the nodes components are referenced to a ground other than v- of the network. figure 16. typical devicenet node these components could include such things as devices with serial ports, parallel ports, rs-232 and rs-485 type ports. as shown in figure 16, power from the network is used only for the transceiver and input (network) side of the optocouplers. isolation of nodes connected to any of the three types of digital feld bus networks is best achieved by using the hcpl-772x/072x optocouplers. for each network, the hcpl-772x/072x satisify the critical propagation delay and pulse width distortion require ments over the tem - perature range of 0 c to +85 c, and power supply volt - age range of 4.5 v to 5.5 v. node/app specific p/can hcpl 772x/072x hcpl 772x/072x transceiver local node supply 5 v reg. network power supply v+ (signal) v? (signal) v+ (power) v? (power) galvanic isolation boundary ac line drain/shield signal power
14 implementing cc-link with the hcpl -772x/072x cc-link (control and communication link) is developed to merge control and information in the low-level net - work (feld network) by pcs, thereby making the mul - tivendor environment a reality. it has data control and message-exchange function, as well as bit control func - tion, and operates at the speed up to 10 mbps. figure 17. recommended cc-link application circuit power supplies and bypassing the recommended cc-link circuit is shown in figure 17. since the hcpl-772x/072x are fully compatible with cmos logic level signals, the optocoupler is con - nected directly to the transceiver. two bypass capacitors (with values between 0.01 f and 0.1 f) are required and should be located as close as possible to the input and output power supply pins of the hcpl-772x/072x. for each capacitor, the total lead length between both ends of capacitor and the power supply pins should not exceed 20 mm. the bypass capacitors are required be - cause of the high speed digital nature of the signals in - side the optocoupler. v dd1 hcpl-7720#500 0.1 v i gnd 1 v dd2 v o gnd gnd 1 rd1 10 k v dd1 (5 v) 0.1 gnd 2 v dd2 (5 v) v dd2 hcpl-7720#500 0.1 v o gnd v dd1 v i gnd sd 0.1 v oe hcpl-2611#560 v o nc + ? nc 0.1 mpu board output 390 hc14 hc14 1 k v oe hcpl-2611#560 v o gnd nc + ? nc 0.1 sdgateon 390 hc14 hc14 1 k 10 k 10 k gnd v dd v dd v cc v cc gnd gnd sn75als181ns fil da db dg sld fg a b y z d de re r
15 implementing devicenet and sds with the hcpl -772x/072x with transmission rates up to 1 mbit/s, both devicenet and sds are based upon the same broadcast-oriented, communica tions protocol the controller area network (can). three types of isolated nodes are recommended for use on these networks: isolated node powered by the network (figure 18), isolated node with transceiver powered by the network (figure 19), and isolated node providing power to the network (figure 20). figure 18. isolated node powered by the network. isolated node with transceiver powered by the network figure 19 shows a node powered by both the network and another source. in this case, the trans ceiver and iso - lated (network) side of the two optocouplers are pow - ered by the network. the rest of the node is powered by the ac line which is very benefcial when an application requires a signifcant amount of power. this method is also desirable as it does not heavily load the network. more importantly, the unique dual-inverting design of the hcpl-772x/072x ensure the network will not lock- up if either ac line power to the node is lost or the node powered-of. specifcally, when input power (v dd1 ) to the hcpl-772x/072x located in the transmit path is eliminat - ed, a recessive bus state is ensured as the hcpl -772x/ 072x output voltage (v o ) go high. isolated node powered by the network this type of node is very fexible and as can be seen in figure 18, is regarded as isolated because not all of its components have the same ground reference. yet, all compo nents are still powered by the network. this node contains two regulators: one is isolated and powers the can controller, node-specifc application and isolated (node) side of the two optocoup lers while the other is non-isolated. the non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers. *bus v+ sensing it is suggested that the bus v+ sense block shown in fig - ure 19 be implemented. a locally powered node with an un-powered isolated physical layer will accumulate er - rors and become bus-of if it attempts to transmit. the bus v+ sense signal would be used to change the boi at - tribute of the devicenet object to the auto-reset (01) value. refer to volume 1, section 5.5.3. this would cause the node to continually reset until bus power was detect - ed. once power was detected, the boi attribute would be returned to the hold in bus-of (00) value. the boi attribute should not be left in the auto-reset (01) value since this defeats the jabber protection capability of the can error confnement. any inexpensive low frequency optical isolator can be used to implement this feature. node/app specific p/can hcpl 772x/072x hcpl 772x/072x transceiver reg. v+ (signal) v? (signal) v+ (power) v? (power) galvanic isolation boundary drain/shield signal power isolated switching power supply network power supply
16 figure 20. isolated node providing power to the network. isolated node providing power to the network figure 20 shows a node providing power to the network. the ac line powers a regulator which provides 5 v local - ly. the ac line also powers a 24 v isolated supply, which powers the network, and another 5 v regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers. this method is recommended when there is a limited number of devices on the net - work, which do not require much power, thus eliminat - ing the need for separate power supplies. figure 19. isolated node with transceiver powered by the network. more importantly, the unique dual-inverting design of the hcpl-772x/072x ensure the network will not lock- up if either ac line power to the node is lost or the node powered-of. specifcally, when input power (v dd1 ) to the hcpl-772x/072x located in the transmit path is eliminat - ed, a recessive bus state is ensured as the hcpl -772x/ 072x output voltage (v o ) go high. node/app specific p/can hcpl 772x/072x hcpl 772x/072x transceiver 5 v reg. v+ (signal) v? (signal) v+ (power) v? (power) galvanic isolation boundary ac line drain/shield signal power isolated switching power supply 5 v reg. devicenet node node/app specific p/can hcpl 772x/072x hcpl 772x/072x transceiver non iso 5 v reg. network power supply v+ (signal) v? (signal) v+ (power) v? (power) galvanic isolation boundary ac line drain/shield signal power *hcpl 772x/072x * optional for bus v + sense
17 power supplies and bypassing the recommended devicenet application circuit is shown in figure 21. since the hcpl-772x/072x are fully compatible with cmos logic level signals, the optocoup - ler is connected directly to the can transceiver. two by - pass capacitors (with values between 0.01 and 0.1 f) are required and should be located as close as possible figure 21. recommended devicenet application circuit implementing profibus with the hcpl-772x/072x an acronym for process fieldbus, profibus is essentially a twisted-pair serial link very similar to rs-485 capable of achieving high-speed communi cation up to 12 mbd. as shown in figure 22, a profibus control ler (pbc) es - tablishes the connec tion of a feld automation unit (con - trol or central processing station) or a feld device to the transmission medium. the pbc consists of the line transceiver, optical isolation, frame character transmit - ter/receiver (uart), and the fdl/app processor with the interface to the profibus user. figure 22. profibus controller (pbc) to the input and output power-supply pins of the hcpl- 772x/072x. for each capacitor, the total lead length be - tween both ends of the capacitor and the power supply pins should not exceed 20 mm. the bypass capac itors are required because of the high-speed digital nature of the signals inside the optocoupler. profibus user: control station (central processing) or field device user interface fdl/app processor transceiver optical isolation uart pbc medium 8 7 6 1 3 5 2 4 v dd1 v in gnd 1 v dd2 v o gnd 2 hcpl-772x hcpl-072x 4 3 2 5 7 1 6 8 gnd 2 v o v dd2 gnd 1 v in v dd1 hcpl-772x hcpl-072x gnd iso 5 v iso 5 v 0.01 f rx0 0.01 f tx0 0.01 f 0.01 f txd canh ref rxd 82c250 v cc gnd rs canl c4 0.01 f + vref linear or switching regulator 5 v 5 v + + r1 1 m c1 0.01 f 500 v d1 30 v 5 v+ 4 can+ 3 shield 2 can? 1 v? galvanic isolation boundary
for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. obsoletes av01-0565en av02-0876en - april 5, 2013 power supplies and bypassing the recommended profibus application circuit is shown in figure 23. since the hcpl-772x/072x are fully compatible with cmos logic level signals, the optocoup - ler is connected directly to the transceiver. two bypass capacitors (with values between 0.01 and 0.1 f) are required and should be located as close as possible to the input and output power-supply pins of the hcpl- 772x/072x. for each capacitor, the total lead length be - tween both ends of the capacitor and the power supply pins should not exceed 20 mm. the bypass capac itors are required because of the high-speed digital nature of the signals inside the optocoupler. being very similar to multi-station rs485 systems, the hcpl-061n optocoupler provides a transmit disable function which is necessary to make the bus free after each master/slave transmission cycle. specifcally, the hcpl-061n disables the transmitter of the line driver by putting it into a high state mode. in addition, the hcpl- 061n switches the rx/tx driver ic into the listen mode. the hcpl-061n ofers hcmos compatibility and the high cmr performance (1 kv/ s at v cm = 1000 v) es - sential in industrial communication interfaces. figure 23. recommended profibus application circuit 1 2 3 8 6 4 7 5 v dd2 v o gnd 2 v dd1 v in gnd 1 hcpl-772x hcpl-072x 8 7 6 1 3 5 2 4 v dd1 v in gnd 1 v dd2 v o gnd 2 hcpl-772x hcpl-072x 5 v 0.01 f 0.01 f 0.01 f 0.01 f r a sn75176b v cc gnd de b 0.01 f iso 5 v 1 m 0.01 f + ? galvanic isolation boundary 5 v iso 5 v re d 1 4 3 2 rx iso 5 v tx 8 7 6 1 3 5 2 4 anode v cc v o gnd 5 v 0.01 f iso 5 v tx enable cathode v e 680 ? hcpl-061n 1, 0 k? 5 7 6 8 rt shield

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